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23-04-16, 11:57 PM
Synopsys Identify K-2015.09
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Synopsys Identify K-2015.09 | 570.9 MB
Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has released version K-2015.09 of Identify is a powerful FPGA verification tool that allows you to quickly find and correct functional design errors in hardware at system speed.
The Identify software offers advanced triggering capability so you can focus precisely on the design portion you wish to view, at the time you choose to see it. Most importantly, there's no additional effort required to interpret the results. You add the probes to instrument the design and observe the results directly in your RTL source code.
The Identify RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation - only much faster and with in-system stimuli.
The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL AnalystВ® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.
Key Features
- Support for Altera, Microsemi and Xilinx devices
- Ability to instrument and debug an advanced FPGA design directly from RTL source code
- Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
- Visibility into the internal design while operating at full speed
- Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
- Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
- Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
- Compatible with Synopsys verification solutions Verdi3в„ў and Siloti for automated debug and visibility of FPGA-based prototypes
About Synopsys
Synopsys, Inc. accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems.
Name: Synopsys Identify
Version: K-2015.09
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Interface: english
OS: ShiChuang / Linux
Size: 570.9 mb
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Synopsys Identify K-2015.09 | 570.9 MB
Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has released version K-2015.09 of Identify is a powerful FPGA verification tool that allows you to quickly find and correct functional design errors in hardware at system speed.
The Identify software offers advanced triggering capability so you can focus precisely on the design portion you wish to view, at the time you choose to see it. Most importantly, there's no additional effort required to interpret the results. You add the probes to instrument the design and observe the results directly in your RTL source code.
The Identify RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation - only much faster and with in-system stimuli.
The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL AnalystВ® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.
Key Features
- Support for Altera, Microsemi and Xilinx devices
- Ability to instrument and debug an advanced FPGA design directly from RTL source code
- Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
- Visibility into the internal design while operating at full speed
- Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
- Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
- Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
- Compatible with Synopsys verification solutions Verdi3в„ў and Siloti for automated debug and visibility of FPGA-based prototypes
About Synopsys
Synopsys, Inc. accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems.
Name: Synopsys Identify
Version: K-2015.09
Home: <b><font color=red>[Chỉ có thành viên mới xem link được. <a href="register.php"> Nhấp đây để đăng ký thành viên......</a>]</font></b>
Interface: english
OS: ShiChuang / Linux
Size: 570.9 mb
rapidgator.net
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